1. Field of the Invention
This invention relates to automatic test equipment used for testing integrated circuits or other electronic devices, and, in particular, to a memory architecture for an automatic test system particularly suited for testing dynamic components or components in which the passing of parameters is necessary.
2. Description of the Prior Art
Many companies manufacture equipment suitable for testing integrated circuits or groups of integrated circuits. For example, the Test Systems Division of Fairchild Camera and Instrument Corporation, assignee of this invention, manufactures a broad line of such equipment, including systems known as Sentry.RTM. systems. Typically, such systems include a group of memories necessary for storing information concerning the tests to be performed on a particular component, the necessary data for performing those tests, the desired output data, and other information, that is, the ones and zeroes for the drivers and comparators in the test apparatus, for functional testing of the device being tested.
Associated with the memories are another set of memories commonly known as sequence control memories. These memories provide control information by defining subroutine patterns, calling subroutines, invoking match modes, providing GO TO's, etc. In addition, the sequence control memories contain address bits for other support memories in the system, including the addresses for the main mask and definition memories. The mask memory is used to control the comparators of the pin electronics circuits, while the definition memory controls the drivers of the pin electronics circuits. Thus, a combination of the contents of the mask and definition memories, toegther with the truth table word from either the main memory or the subroutine memory, determine three bits of functional data per pin for the device under test.
Continuing advances in the complexity and capability of integrated circuits, however, have resulted in a need for a more flexible memory architecture. For example, in testing many dynamic components, several hundred thousand test cycles may be needed, and consequently more masks, definitions or vectors are required than the memories of the system are capable of storing. Typically, in some prior art automatic systems, this restriction has necessitated completely stopping testing of the component to enable reloading the necessary memories. Of course, after reloading the memories, a test sequence must be provided to bring the dynamic component to a known state before proceeding with further testing.
Another limitation in present test systems which has become increasingly undesirable with advancements in the state of microprocessor design is the difficulty to pass parameters from the main program to the subroutines. For example, in testing a typical microprocessor, the subroutine will contain the truth table which is constant for a particular microprocessor cycle, such as the instruction fetch operation, and it is desirable to pass to the formatter, in conjunction with the subroutine call, the location from which the fetch is to be performed. The use of such subroutines and parameter passing enables substantial compaction of data stored in the main memory when compared to the straight-line mode. The inability to pass such parameters therefore results in a need for larger memories, with the accompanying slower access times and increased cost.